;PTH Interrupt Programming with AsmIDE (or MiniIDE) on Dragon12+ with D-Bug12 ;An LED on PORTB Toggles continuously while waiting for AN Interrupt from PTH ;Buzzer will sound for short period of time if any of DIP Switches on PTH is activated (going from H-to-L). ;The Interrupts go to the Interrupt vector table in $FFFF-FFxx ROM addres area. ;However,the D-Bug12 redirects them to RAM space area of $3Exx-3Exx ;We must redirect them from these areas to our ISR. ;Written and tested by Mazidi. See Chapter 11 of HCS12 textbook by Mazidi & Causey #include "C:\Reg9s12.H" ;----------------------USE $1000-$2FFF for Scratch Pad and Stack R1 EQU $1001 R2 EQU $1002 R3 EQU $1003 R4 EQU $1004 ;how long to sound the buzzer. During the buzzer sound LED stops toggleing. Why? ;code section ORG $2000 Entry: LDS #$2000 ;Stack LDAA #$FF STAA DDRB ;MAKE PORTB AN OUTPUT PORT BSET DDRJ,%00000010 ;MAKE PORTJ1 AN OUTPUT PIN BCLR PTJ,%00000010 ;TURN OFF PORTJ1 TO ALLOW LEDs ON PORTB TO SHOW DATA BSET DDRT,%00100000 ;PTT5 as Output pin for buzzer ; INTERRUPT SET-UP FOR PTH Interrupt LDAA #0 ;PTH as input STAA DDRH LDAA #$FF ; STAA PIEH ;Enable PTH interrupt LDAA #$0 STAA PPSH ;Make PTH Interrupt level trigger. CLI ;ENABLE INTERRUPTS GLOBALLY ;-------Toggle PB0 forever and wait for interrupt BACK BSET PORTB,%00000001 ;PORTB0=1 JSR DELAY BCLR PORTB,%00000001 ;PORTB0=0 JSR DELAY BRA BACK ;Keep Toggling PB0, while waiting for Interrupt to come in ;---end of main program ;---PTH INTERRUPT SERVICE ROUTINE. Sound the buzzer for short period of time every time any of PTH goes from H-to-L PTH_ISR LDAA #5 STAA R4 ;how long the buzzer should sound OVER BSET PTT, %00100000 JSR DELAY BCLR PTT, %00100000 JSR DELAY DEC R4 BNE OVER LDAA #$FF ;Clear the PTH Interrupt flags for next round STAA PIFH ;Writing HIGH will clear the Interrupt Flag. RTI ;Return from ISR to main program ;----------DELAY DELAY PSHA ;Save Reg A on Stack LDAA #100 ; STAA R3 ; ;--1 msec delay. The D-Bug12 works at speed of 48MHz with XTAL=8MHz on Dragon12+ board ;Freq. for Instruction Clock Cycle is 24MHz (1/2 of 48Mhz). ;(1/24MHz) x 10 Clk x240x10=1 msec. Overheads are excluded in this calculation. L3 LDAA #10 STAA R2 L2 LDAA #240 STAA R1 L1 NOP ;1 Intruction Clk Cycle NOP ;1 NOP ;1 DEC R1 ;4 BNE L1 ;3 DEC R2 ;Total Instr.Clk=10 BNE L2 DEC R3 BNE L3 ;-------------- PULA ;Restore Reg A RTS ;------ ;************************************************************** ;In HCS12, the Interrupts go to the Interrupt vector table in $FFFF-FFxx ROM addres area. ;However,the D-Bug12 redirects them to RAM space area of $3Exx-3Exx ;We must redirect them from these areas to our ISR. ; ;* Interrupt Vector Table Addresses for D-Bug12 are on page 365 of Mazidi & Causey HCS12 textbook ;************************************************************** ORG $3E4C ;Vector table location for PTH interupt is 3E4C (See page 365 of Mazidi & Causey HCS12 textbook) DC.W PTH_ISR