;Displaying ATD0 channel 7 (POT) on LEDs of PORTB for Dragon12+ Trainer Board 
;with HCS12 D-Bug12 Program installed. This code is for AsmIDE and MiniIDE
;Modified from Program 13-1 of HCS12 book by Mazidi & Causey 
;In Dragon12+ PLL=48MHz. 48MHz/2=24MHz, Divivde by 24 to get 1MHz for conversion freq. 
;ATD0 channel 7 (AN07) is connected to VR2 Pot Trimer (Blue POT above right side of breadboard)
;Change the POT to see the changes on LEDs of PORTB

#include "C:\Reg9s12.H"
;----------------------USE $1000-$2FFF for Scratch Pad and Stack
R1      EQU     $1001
R2      EQU     $1002
R3      EQU     $1003

;code section
        ORG   $2000     ;
Entry:
	LDS     #$2000    ;Stack
        LDAA    #$FF
        STAA    DDRB		;Make PORTB output
  ;PTJ1 controls the LEDs connected to PORTB (For Dragon12+ ONLY)
        LDAA    #$FF      	
	STAA    DDRJ   	;Make PORTJ output, (Needed by Dragon12+) 
	LDAA    #$0
	STAA    PTJ   	;Turn off PTJ1 to allow the LEDs on PORTB to show data (Needed by Dragon12+) 
;
;-------Get data fron Chan 7 of ATD0 and put it on PORTB

        MOVB	#$80,ATD0CTL2  
	JSR	DELAY	
	MOVB	#$08,ATD0CTL3
	MOVB	#$EB,ATD0CTL4    ;8-bit resolu, 16-clock for 2nd phase,
                               ;prescaler of 24 for Conversion Freq=1MHz  
     
H1 	MOVB	#$07,ATD0CTL5	;Chan 7 of ATD0 (use left-justified) for POT
				;notice ADC value is in high byte of result reg since low-byte is not supported by the asembler  

H2	BRCLR ATD0STAT,$80,H2
	LDAA	ADR00H		;get the ADC result from High bye reg. 
	STAA	PORTB		 	 
	JSR   DELAY             ;Optional		 
  
        BRA   H1                ;Keep reading the ADC
   
  
;----------DELAY
DELAY

        PSHA		;Save Reg A on Stack
        LDAA    #1		  
        STAA    R3		
;--0.1 msec delay. The D-Bug12 works at speed of 48MHz with XTAL=8MHz on Dragon12+ board
;Freq. for Instruction Clock Cycle is 24MHz (1/2 of 48Mhz). 
;(1/24MHz) x 10 Clk x240x1=1 msec. Overheads are excluded in this calculation.         
L3      LDAA    #1
        STAA    R2
L2      LDAA    #240
        STAA    R1
L1      NOP         ;1 Intruction Clk Cycle
        NOP         ;1
        NOP         ;1
        DEC     R1  ;4
        BNE     L1  ;3
        DEC     R2  ;Total Instr.Clk=10
        BNE     L2
        DEC     R3
        BNE     L3
;--------------        
        PULA			;Restore Reg A
        RTS
;-------------------